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ESDALC6V1W5
QUAD TRANSILTM ARRAY FOR ESD PROTECTION
Application Specific Discretes A.S.D.
MAIN APPLICATIONS Where transient overvoltage protection in ESD sensitive equipment is required, such as : Computers Printers Communication systems and cellular phones Video equipment Set top boxes
s s s s s
FEATURES 4 unidirectional TRANSILTM functions. ESD Protection: IEC61000-4-2 level 4 Breakdown voltage VBR = 6.1V min Low leakage current < 1A @ 3 Volts Low capacitance device
s s s s s
SOT323-5L
FUNCTIONAL DIAGRAM
DESCRIPTION The ESDALC6V1W5 is a 4-bit wide monolithic suppressor which is designed to protect component connected to data and transmission lines against ESD. It clamps the voltage just above the logic level supply for positive transients, and to a diode drop below ground for negative transients. BENEFITS High ESD protection level : up to 25 kV. Capacitance: 12pF @ 0V Typ. High integration. Suitable for high density boards.
s s s s
I/01 GND I/02
I/04
I/03
COMPLIES WITH THE FOLLOWING STANDARDS :
s
s
IEC61000-4-2 level 4: 15 kV (air discharge) 8 kV (contact discharge) MIL STD 883C-Method 3015-6 : class 3. (human body model) 25kV (HBM)
June 2002 - Ed: 4A
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ESDALC6V1W5
ABSOLUTE MAXIMUM RATINGS (Tamb = 25C) Symbol VPP Parameter Test conditions Value 25 15 8 25 150 - 55 to + 150 - 40 to + 150 Unit kV
ESD discharge - MIL STD 883E - Method 3015-7 IEC61000-4-2 air discharge IEC61000-4-2 contact discharge Peak pulse power (8/20 s) Junction temperature Storage temperature range Operating temperature range
PPP Tj Tstg Top
W C C C
ELECTRICAL CHARACTERISTICS (Tamb = 25C) Symbol VRM VBR VCL IRM IPP C Rd Parameter Stand-off voltage Breakdown voltage Clamping voltage Leakage current Peak pulse current Capacitance per line Dynamic resistance
slope : 1 / Rd IPP VCL VBR VRM IRM IR
I
V
Types min.
VBR
@ max.
IR
IRM max.
@
VRM
Rd typ. note 1
T max. note 2 10 /C 6
-4
C typ. 3V bias pF 7.5
C max. 3V bias pF 9.5
V
V 7.2
mA 1
A 1
V 3
m 1100
ESDALC6V1W5
6.1
Note 1 : Square pulse Ipp = 15A, tp=2.5s. Note 2 : VBR = T* (Tamb -25C) * VBR (25C)
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Fig. 1: Relative variation of peak pulse power versus initial junction temperature.
Ppp[Tj initial] / Ppp [Tj initial = 25C]
1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 25 50 75 100 125 150 175
Fig. 2: Peak pulse power versus exponential pulse duration.
Ppp(W)
100
Tj initial = 25C
Tj(C)
10 1
tp(s)
10 100
Fig. 3: Junction capacitance versus reverse voltage applied (typical values).
C(pF)
14 12 10 8 6
F=1MHz Vosc=30mVRMS Tj=25C
Fig. 4: Clamping voltage versus peak pulse current (maximum values, rectangular waveform).
Ipp(A)
100.0
10.0
1.0
4 2
VR(V)
0 0 1 2 3 4 5
Vcl(V)
0.1 0 10 20 30 40
tp=2.5s Tj initial =25C
50
60
Fig. 5: Relative variation of leakage current versus junction temperature (typical values).
IR [Tj] / IR [Tj=25C]
100
Fig. 6: Application example
I/02
Connector
I/01 I/04 I/03
IC to be protected
10
Tj(C)
1 25 50 75 100 125
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ESDALC6V1W5
TECHNICAL INFORMATION 1. ESD protection by ESDALC6V1W5 With the focus of lowering the operation levels, the problem of malfunction caused by the environment is critical. Electrostatic discharge (ESD) is a major cause of failure in electronic systems. As a transient voltage suppressor, ESDALC6V1W5 is an ideal choice for ESD protection by suppressing ESD events. It is capable of clamping the incoming transient to a low enough level such that any damage is prevented on the device protected by ESDALC6V1W5. ESDALC6V1W5 serves as a parallel protection elements, connected between the signal line and ground. As the transient rises above the operating voltage of the device, the ESDALC6V1W5 becomes a low impedance path diverting the transient current to ground. The clamping voltage is given by the following formula: VCL = VBR + Rd.IPP As shown in figure A1, the ESD strikes are clamped by the transient voltage suppressor.
Fig. A1: ESD clamping behavior
RG VG
IPP Rd V(i/o) VBR RL O AD
Device to be protected
ESD surge
ESDALC6V1W5
To have a good approximation of the remaining voltages at both Vi/o side, we provide the typical dynamical resistance value Rd. By taking into account the following hypothesis: Rg > Rd and Rload > Rd we have: V V (i / o ) = V BR + Rd x g Rg The results of the calculation done Vg = 8kV, Rg = 330 (IEC61000-4-2 standard), VBR = 6.1V (min) and Rd = 1.1 (typ.) give: V (i / o ) = 32,8Volts This confirms the very low remaining voltage across the device to be protected. It is also important to note that in this approximation the parasitic inductance effect was not taken into account. This could be a few tenths of volts during a few ns at the Vi/o side.
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ESDALC6V1W5
Fig. A2: ESD test board Fig. A3: ESD test configuration
TEST BOARD
V(i/o) V(i /o)
I/O1, I/O2, I/O3 or I/O4 8kV ESD Contact discharge B2
V(i/o)
The measurements done here after show very clearly (Fig. A4) the high efficiency of the ESD protection: the clamping voltage V(i/o) becomes very close to +VBR (positive way, Fig. A4a) and -VBR (negative way, Fig. A4b).
Fig. A4: Remaining voltage during ESD surge
V(i/o)
V(i/o)
a: Response in the positive way
b: Response in the negative way
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ESDALC6V1W5
CROSSTALK BEHAVIOR Fig. A5: Crosstalk phenomenon
RG1
Line 1
VG1
RL1
RG2
1VG1 + 12VG2
Line 2
VG2
RL2
2VG2 + 21VG1
DRIVERS
RECEIVERS
The crosstalk phenomena are due to the coupling between 2 lines. Coupling factors ( 12 or 21 ) increase when the gap across lines decreases, particularly in silicon dice. In the example above, the expected signal on load RL2 is 2VG2, in fact the real voltage at this point has got an extra value 21VG2. This part of the VG1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be taken into account when the drivers impose fast digital data or high frequency analog signals. The perturbed line will be more affected if it works with low voltage signal or high load impedance (few k)
Fig. A6: Analog crosstalk measurements
RF TEST BOARD TEST BOARD
I/O4
To Port1
To Port2
I/O1
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ESDALC6V1W5
Fig. A7: Typical analog crosstalk measurements.
ESDALC6V1W5 : typical analog crosstalk response
0.00 dB -10.00 -20.00 -30.00 -40.00 -50.00 -60.00 -70.00 -80.00 -90.00 -100.0 1.0M 3.0M 10.0M 30.0M 100.0M f/Hz 300.0M 1.0G 3.0G
Figure A6 gives the measurement circuit for the analog crosstalk application. In figure A7, the curve shows the effect of the line I/O1 on the line I/O4. In usual frequency range of analog signals (up to 100MHz) the effect on disturbed line is less than -60dB. Fig. A8: Digital crosstalk measurements configuration.
I/O1
Fig. A9: Digital crosstalk results.
unloaded
rise time: t10-90% = 3ns
VG1 0 - 3kV pulse generator F= 5MHz tR = 3ns GND 21VG1 unloaded I/O4
VG1
21VG1
crosstalk
Figure A8 shows the measurement circuit used to quantify the crosstalk effect in a classical digital application. Figure A9 shows that in such a condition, the impact on the disturbed line is less than 50 mV peak to peak. No data disturbance was noted on the concerned line. The measurements performed with falling edges give an impact within the same range.
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ESDALC6V1W5
Fig. A10: Aplac model
Lbond I/O1 caphole
D6V1
D6V1
Lbond I/O4
Cz 9.2pF Rs 100m Lbond 1.2nH Lhole 380pH Caphole 0.2pF Rhole 450m Model D6V1 BV = 7 IBV = 1m CJO = Cz M = 0.3333 RS = 1 VJ = 0.6 TT = 100n
Rhole Lhole
Lbond I/O2
D6V1
D6V1
Lbond I/O3
ORDER CODE
ESDA LC 6V1
ESD ARRAY LOW CAPACITANCE VBR min
Ordering type ESDALC6V1W5 Marking C61 Package SOT323-5L
W5
PACKAGE: SOT323-5L
Weight 5.4 mg.
Base qty 3000
Delivery mode Tape & reel
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ESDALC6V1W5
PACKAGE MECHANICAL DATA SOT323-5L DIMENSIONS
A A2
REF.
Millimeters Min. Max. 1.1 0.1 1 0.3 0.18 2.2 1.35
Inches Min. 0.031 0 0.031 0.006 0.004 0.071 0.045 Max. 0.043 0.004 0.039 0.012 0.007 0.086 0.053
A1
A A1
D e e
0.8 0 0.8 0.15 0.1 1.8 1.15
A2 b c D
H
E
E e
0.65 Typ. 1.8 0.1 2.4 0.4
0.026 Typ. 0.071 0.004 0.094 0.016
Q1 c b
H Q1
FOOT PRINT (in millimeters)
0.3mm
Mechanical specifications Lead plating Tin-lead 5m min. 25 m max. Sn / Pb (70% to 90% Sn) 10m max. Molded epoxy UL94,V0 Lead plating thickness
2.9mm
1mm
Lead material Lead coplanarity
1mm
Body material Epoxy meets
0.35mm
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - Printed in Italy - All rights reserved. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com 9/9

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